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DFT Engineers
Technical Requirements
3~6
years of Design-For-Test (DFT) experience
Experience in architecting and designing testability logic for ~2 ASICs
Working
Knowledge of both memory and logic BIST design and implementation.
Familiarity with various fault models (stuck-at,
transition, IDDQ) and their appropriate use in achieving high fault coverage in complex, multiple clock domain IC designs
Detailed
knowledge of JTAG and Boundary Scan design and implementation, especially in designs with multiple, complex I/O cell types.
Experience using scan insertion tools such as Synopsys DFT Compiler, Mentor DFT Advisor, or Logic Vision
Experience
with ATPG and tools such as Synopsys Tetramax, Mentor Fastscan, or Logic Vision
DFT, ATPG, Synopsys Tetramax, JTAG
Additional
Technical Requirements desired
Scripting in PERL and/or Tcl/Tk
Hands-on experience with signoff flows
for ASIC or COT foundries a plus
Other requirements
Ability to speak or read in Japanese language will
be a big +ve
Readiness for travel to Japan on deputation
Excellent communication and Presentation skills,
Oral and Written
Client friendly, team player & with good analytical skills
Initiative, Self-motivated,
Self-Learning and ability to mentor
JOBLOCATION:JAPAN
Regards,
Alankar
Executive,HumanResources
eQURA
consulting
Mobile :9845494350
Direct : 91-80-51155360//51155361 Ext 15
Fax : 91-80-51153937
Email : alankar@equra.com
URL
: www.equra.com
Don't ever stop loving,don't ever stop believing,
don't ever stop dreaming your dreams
Live Your
Dreams...........
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